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Data Sheet
ADE7854/ADE7858/ADE7868/ADE7878
Address
0xE705
Register
Name
CFCYC
R/W 1
R/W
Bit
Length
8
Bit Length
During
Communication 2
8
Type 3
U
Default
Value 4
0x01
Description
Number of CF pulses between two
consecutive energy latches. See the
Synchronizing Energy Registers with
CFx Outputs section.
0xE706
0xE707
HSDC_CFG
Version
R/W
R
8
8
8
8
U
U
0x00
HSDC configuration register. See Table 53.
Version of die.
0xEBFF
Reserved
8
8
This address can be used in manipulating
the SS/HSA pin when SPI is chosen as
the active port. See the Serial Interfaces
section for details.
0xEC00
LPOILVL
R/W
8
8
U
0x07
Overcurrent threshold used during
PSM2 mode ( ADE7868 and ADE7878
only). See Table 54 in which the register
is detailed.
0xEC01
CONFIG2
R/W
8
8
U
0x00
Configuration register used during
PSM1 mode. See Table 55.
1
2
3
4
R is read, and W is write.
32 ZP = 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE = 24-bit signed register that
is transmitted as a 32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.
U is unsigned register, and S is signed register in twos complement format.
N/A is not applicable.
Table 34. HPFDIS Register (Address 0x43B6)
Bit
Default
Location
23:0
Value
00000000
Description
When HPFDIS = 0x00000000, then all high-pass filters in voltage and current channels are enabled. When the
register is set to any nonzero value, all high-pass filters are disabled.
Table 35. IPEAK Register (Address 0xE500)
Bit Location
23:0
24
25
26
31:27
Bit Mnemonic
IPEAKVAL[23:0]
IPPHASE[0]
IPPHASE[1]
IPPHASE[2]
Default Value
0
0
0
0
00000
Description
These bits contain the peak value determined in the current channel.
When this bit is set to 1, Phase A current generated IPEAKVAL[23:0] value.
When this bit is set to 1, Phase B current generated IPEAKVAL[23:0] value.
When this bit is set to 1, Phase C current generated IPEAKVAL[23:0] value.
These bits are always 0.
Table 36. VPEAK Register (Address 0xE501)
Bit Location
23:0
24
25
26
31:27
Bit Mnemonic
VPEAKVAL[23:0]
VPPHASE[0]
VPPHASE[1]
VPPHASE[2]
Default Value
0
0
0
0
00000
Description
These bits contain the peak value determined in the voltage channel.
When this bit is set to 1, Phase A voltage generated VPEAKVAL[23:0] value.
When this bit is set to 1, Phase B voltage generated VPEAKVAL[23:0] value.
When this bit is set to 1, Phase C voltage generated VPEAKVAL[23:0] value.
These bits are always 0.
Table 37. STATUS0 Register (Address 0xE502)
Bit
Location
0
Bit Mnemonic
AEHF
Default Value
0
Description
When this bit is set to 1, it indicates that Bit 30 of any one of the total active energy
registers (AWATTHR, BWATTHR, or CWATTHR) has changed.
1
FAEHF
0
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental active
energy registers, FWATTHR, BFWATTHR, or CFWATTHR, has changed. This bit is always 0
for ADE7854 , ADE7858 , and ADE7868 .
2
REHF
0
When this bit is set to 1, it indicates that Bit 30 of any one of the total reactive energy
registers (AVARHR, BVARHR, or CVARHR) has changed. This bit is always 0 for ADE7854 .
Rev. H | Page 85 of 100
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